1. Field of the Invention
This invention relates to semiconductor devices and more particularly to neuron MOSFET devices.
2. Description of Related Art
Heretofore, in semiconductor devices with plural input circuits, a weighted sum of input signals has been achieved by employing capacitors with different capacitor areas with the same interpolysilicon oxide thickness which may require large capacitor area to obtain different weighting factors.
The neuron MOSFET (neuMOS) is so named because it is considered to be analogous in function to a biological neuron. The neuMOS includes doubler polysilicon structures utilized as coupling capacitor. See Shibata et al "Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", IEEE Transactions on Electron Devices, Vol. 39, No. 6, p 1444-1455 (June, 1992)
U.S. Pat. No. 5,215,934 of Tzeng shows a different thickness depending upon where the ion implantation is present or is absent from the silicon surface with argon, boron, antimony, arsenic, or any group III or IV dopant applied for enhancing the rate of oxidation in silicon which has been damaged by the process of implantation of such dopants. The variable thickness is employed for providing a two tiered tunnel oxide upon which a floating gate and control gate are formed across the two tiers for the purpose of as stated at Col. 7, lines 11-12 "reducing drain disturbance in EEPROM arrays . . . " It also states at Col. 2, lines 52-54 "it is also desired to thicken the gate oxide near the drain region to reduce drain disturbance phenomena . . . "
U.S. Pat. No. 5,038,184 of Chiang et al shows a thin film varactor structure.
U.S. Pat. No. 5,119,267 of Sano et al, U.S. Pat. No. 5,018,000 of Yamada et al, U.S. Pat. No. 4,890,191 of Rokos; U.S. Pat. No. 4,841,320 of Aso; U.S. Pat. No. 4,805,071 of Hutter et al; and U.S. Pat. No. 4,211,941 of Schade show processes for making capacitors. However, these processes fail to increase capacitance without increasing the area required.
In prior technology: ##EQU1##